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bk1086/88 rev.1.0 copyright?2010 by beken corporation bk1086/88 beken confidential. information contained herein is covere d under non-disclosure agreement (nda). b roadcast am/fm/sw/lw r adio r eceiver features ? worldwide 64~108 mhz fm band support ? worldwide 520~1710khz am band support ? sw band support(2.3-21.85mhz, BK1088 only) ? lw band support(153-279khz,BK1088 only) ? automatic gain control(agc) ? automatic frequency control(afc) ? digital fm stereo decoder ? automatic fm stereo/mono blend ? automatic noise suppression ? 50us/75us de-emphasis ? rds/rbds decoder ? 2.4 ~ 5.5 v supply voltage ? wide range reference clock support ? 32.768khz crystal oscillator ? 4x4 mm 24-pin qfn package applications ? table and portable radios ? cd/dvd players ? modules general description the bk1086/88 am/fm receiver employs a low-if architecture, mixed signal image rejection and all digital demodulation technology. the station scan of bk1086/88 searches radio stations based on both the channel rssi estimation and signal quality assessment, increases the number of receivable stations while avoids false stops. bk1086/88 enables fm/am/sw/lw radio reception with low power, small board space and minimum number of external component. qfn 24 pin assignments (top view) functional block diagram gnd fmi rfgnd ami gnd nc mode s e n sclk sdio rclk vio vd gnd rout lout gnd va gpio3 gpio2 gpio1 nc nc gnd 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 19 20 21 22 23 24 gnd pad bk1086/88 am lna mixer 32.768khz dpll reg adc 0/90 control interface dac lout rout vdd mcu vio sclk sen sdio gpio rfgnd auto tune apll pga bk1086/88 pga mw ant mixer fm lna fm ant adc dac rds dsp free datasheet http://www..net/
bk1086/88 proprietary and confidential page 2 of 30 1 table of contents 1 table of contents.............................................................................................................. .... 2 2 functional description ......................................................................................................... 3 2.1 fm receiver ................................................................................................................ ... 3 2.2 am receiver................................................................................................................ ... 3 2.3 interface bus .............................................................................................................. .... 4 2.3.1 3-wire bus mode ........................................................................................................ 4 2.3.2 i2c bus mode............................................................................................................. 4 2.4 stereo audio processing................................................................................................ 5 2.5 seek/tune system ......................................................................................................... 5 2.6 gpio output ................................................................................................................ ... 6 2.7 rds processor.............................................................................................................. .6 2.8 reference clock............................................................................................................ .7 2.9 initialization sequence ................................................................................................... 7 3 design specification........................................................................................................... .. 8 3.1 recommended operating conditions............................................................................ 8 3.2 power consumption specification ................................................................................. 8 3.3 receiver characteristics ................................................................................................ 9 3.4 i2c control interface characteristics ........................................................................... 11 3.5 3-wire control interface characteristics ...................................................................... 12 4 register definition ............................................................................................................ .. 13 5 pin assignment................................................................................................................. .. 23 6 typical application schematic.......................................................................................... 24 7 package information........................................................................................................... 2 5 8 solder reflow profile.......................................................................................................... 27 9 order information .............................................................................................................. .28 10 additional reference resource ........................................................................................ 29 11 revision history............................................................................................................... ... 30 free datasheet http://www..net/
bk1086/88 proprietary and confidential page 3 of 30 2 functional description figure1. functional block diagram 2.1 fm receiver the receiver employs a digital low-if architecture that reduces external components, and integrates a low noise amplifier (lna) supporting the worldwide fm broadcast band (64 to 108mhz), an automatic gain control (agc) circuit controls the gain of the lna to optimize sensitivity and rejection of strong interferers, an image- reject mixer down converts the rf signal to low-if, the mixer output is amplified by a programmable gain control (pga), and digitized by a high resolution analog-to-digital converters (adcs). an audio dsp finishes the channel selection, fm demodulation, stereo mpx decoder and output audio signal. the mpx decoder can autonomous switch from stereo to mono to limit the output noise. 2.2 am receiver bk1086/88 supports worldwide am band reception by a digital low-if architecture with minimum number of external components. this architecture allows for high-pr ecision filtering, offering excellent selectivity and noise suppression. similar to the fm receiver, the integrated lna and agc optimize sensitivity and rejection of strong interferers allowing better reception of weak stations. the bk1086/88 provides highly accurate digital am tuning without factory adjustments. to offer maximum flexibility, the receiver supports a wide range of ferrite loop sticks from 180?600 h for mw band.. am lna mixer 32.768khz dpll reg adc 0/90 control interface dac lout rout vdd mcu vio sclk sen sdio gpio rfgnd auto tune apll pga pga mw ant mixer fm lna fm/sw ant adc dac rds dsp free datasheet http://www..net/
bk1086/88 proprietary and confidential page 4 of 30 2.3 interface bus the bk1086/88 supports 3-wire and i 2 c control interface, with up to 2.5 mhz clock speed. user could select either of them by setting the st ate of mode pin. bk1086/88 will use i2c interface for mode=0 or 3-wire interface for mode =1. bk1086/88 always latches data at the sclk rising edge and outputs its data at sclk falling edge. for mcu, data should be always written at the falling edge of sclk, and read out at the rising edge of sclk. 2.3.1 3-wire bus mode when selecting 3-wire mode, user must set mode = 1. 3-wire bus mode uses sclk, sdio and sen pins. a transaction begins when user drives sen low. next, user drives an 8-bit command serially on sdio, which is captured by bk1086/88 on rising edges of sclk. the command consists of a 7- bit start register address, followed by a read/write bit (read = 1, write = 0). 2.3.2 i2c bus mode when selecting i2c mode, user must set mode = 0. i2c bus mode only uses sclk and sdio pins. a transaction begins with the start condition, which occurs when sdio falls while sclk is high. next, user drivers an 8-bit device id serially on sdio, which is captured by bk1086/88 at the rising edge of sclk. the device id of bk1086/88 is 0x80. after driving the device id, user drives an 8-bit control word on sdio. the control word consists of a 7-bit start register address, followed by a read/write bit (read = 1, write = 0). for i2c host reading, the host must give an ack to bk1086/88 after each byte access, and should give a nack to bk1086/88 after last byte read out. for stable communication, the rising edge time of sclk should be less than 200ns. sclk sen sdio d[15], d[14], , d[0] c o m m a n d data[addr] data[addr+1] data[addr+n] 0.5t clk 0.5t clk d[15:0] d[15:0] 0.5t clk addr[6:0] + r/w figure 2. 3-wire interface diagram sclk sdio deviceid start addr + r/w data[addr] high byte data[addr] low byte data[addr+n] high byte data[addr+n] low byte a c k n a c k device id stop addr[6:0] + r/w d[15:8] d[7:0] d[15:8] d[7:0] 0.5t clk 0.5t clk ack a c k 0.5t clk figure 3. i2c interface diagram free datasheet http://www..net/
bk1086/88 proprietary and confidential page 5 of 30 2.4 stereo audio processing the output of the fm demodulator is a stereo multiplexed (mpx) signal. mpx signal format consists of left + right (l+r) audio, left ? right (l?r) audio, a 19 khz pilot tone, and rds data. the bk1086/88 has integrated stereo decoder automatically decodes the mpx signal. the 0 to 15 khz (l+r) signal is the mono output of the fm tuner. stereo is generated from the (l+r), (l-r), and a 19 khz pilot tone. the pilot tone is used as a reference to recover the (l-r) signal. separate left and right channels are obtained by adding and subtracting the (l+r) and (l-r) signals, respectively. adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (l+r) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. the signal level range over which the stereo to mono blending occurs can be adjusted by setting the blndadj [1:0] register. stereo/mono status can be monitored with the st register bit and mono operation can be forced with the mono register bit and stereo operation can be forced with the stereo register bit. bk1086/88 uses pre-emphasis and de- emphasis to improve the signal-to-noise ratio of fm receivers by reducing the effects of high frequency interference and noise. when the fm signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. all fm receivers incorporate a de-emphasis filter which attenuates high freque ncies to restore a flat frequency response. two time constants, 50 or 75 s, are used in various regions. the de-emphasis time constant is programmable with the de bit. high-fidelity stereo digital-to-analog converters (dacs) drive analog audio signals onto the lout and rout pins. the audio output may be muted with the dmute bit. volume can be adjusted digitally with the volume [4:0] bits. the soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. the soft mute attack and decay rate can be adjusted with the smuter [1:0] bits where 00 is the fastest setting. the soft mute attenuation level can be adjusted with the smutea [1:0] bits where 00 is the most attenuated. the soft mute disable (dsmute) bit may be set high to disable this feature. 2.5 seek/tune system in fm mode, channel spacing of 10 50, 100 or 200 khz is selected with bits space [1:0]. the channel is selected with bits chan [14:0]. the bottom of the band is set to 64 mhz, 76 mhz or 87 mhz with the bits band [1:0]. the tuning operation begins by setting the tune bit. after tuning completes, the seek/tune complete (stc) bit will be set and the rssi level is available by reading bits rssi [6:0]. the tune bit must be set low after the stc bit is set high in order to prepare for the next tune operation and clear the stc bit. seek tuning searches up or down for a channel with rssi greater than the seek threshold set with the seekth [6:0] bits and snr greater than the snr threshold set with the sksnr [6:0] bits. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 6 of 30 in addition, an optional afcrl and/or impulse noise detector may be used to qualify valid stations. the afcrl detector is set by skafcrl and the skcnt [3:0] bits set the impulse noise threshold. using the extra seek qualifiers can reduce false stops and, in combination with lowering the rssi seek threshold, increase the number of found stations. two seek modes are available. if the seek mode (skmode) bit is low when seeking process is initiated, the device seeks through the band, wraps from one band edge to the other, and continues seeking. if the seek operation was unable to find a channel, the seek failure/band limit (sf/bl) bit will be set high and the device will return to the channel selected before the seek operation began. if the skmode bit is high when seeking process is initiated, the device seeks through the band until the band limit is reached and the sf/bl bit will be set high. a seek operation is initiated by setting the seekup and seek bi ts. after the seek operation completes, the stc bit will be set, and the rssi level as well as the tuned channel number are available by reading bits rssi [7:0] and bits readchan [14:0]. during a seek operation readchan [14:0] is also updated and may be read to supervise the seeking progress. the stc bit is set after the seek operation completes. the channel is valid if the seek operation completes and the sf/bl bit is set low. note that if the afcrl bit is set or the snr and rssi are lower than the thresholds, the audio output is muted as in the soft mute case discussed in stereo audio processing section. the seek bit should be set low after the stc bit is set high in order to prepare for the next seek operation as well as clearing the stc and sf/bl bits. the seek operation may be aborted by setting the seek bit low at any time. the device can be configured to generate an interrupt on gpio2 when a tune or seek operation completes. setting the seek/tune complete (stcien) bit and gpio2 [1:0] = 01 will configure gpio2 for a 5 ms low interrupt when the stc bit is set by the device. the am mode tuning system algorithm is same as fm mod 2.6 gpio output the bk1086/88 has three gpio pins. the function of gpio pins could be programmed with bits gpio1 [1:0], gpio2 [1:0], gpio3 [1:0], gpio2/3 pins can be used as interrupt request pins for the seek/tune or rds ready functions and as a stereo/mono indicator respectively. gpio functionality is available regardless of the state of the va and vd supplies, or the enable and disable bits. 2.7 rds processor the bk1086/88 implements an rds processor for symbol decoding, block synchronization, error detection, and error correction. set the rdsen=1 will enable rds reception, and set rdsdec=1 will enable automatic error correction. after error check and processing, if a correct rds frame is received, the received block will be placed at rdsa, rdsb, rdsc and rdsd registers and rds ready bit rdsr will be set. when rdsien is enabled, a 5 ms active low interrupt will be issued on gpio2. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 7 of 30 2.8 reference clock the bk1086/88 accepts wide range, from 32.768 khz to 38.4 mhz, reference clock input to the rclk pin. for frequency less than 4 mhz, it must be multiplier of 32.768 khz. the bk1086/88 also support 32.768khz crystal oscillator. low quality reference clock with 200ppm is acceptable. 2.9 initialization sequence to initialize bk1086/88: 1. supply vio. 2. supply va and vd. note that va and vd could be supplied at the same time of vio supplied. 3. provide rclk. 4. set the enable bit high and the disable bit low to power up bk1086/88. to power down bk1086/88: 1. set the enable bit high and the disable bit high to place bk1086/88 in power down mode. note that all register states are maintained as long as vio is supplied. 2. (optional) remove rclk. 3. remove va and vd as needed. to power up bk1086/88 (after power down): 1. note that vio is still supplied in this scenario. if vio is not supplied, refer to bk1086/88 initialization procedure above. 2. supply va and vd. 3. provide rclk. 4. set the enable bit high and the disable bit low to power up bk1086/88. 5. 4 3 vio supply va/vd supply rclk pin enable bit 1 2 figure 4 initialization sequence free datasheet http://www..net/
bk1086/88 proprietary and confidential page 8 of 30 3 design specification 3.1 recommended oper ating conditions table 1 recommended operating conditions parameter symbol test condition min typ max unit digital supply voltage v d 2.4 ? 5.5 v analog supply voltage v a 2.4 ? 5.5 v interface supply voltage v io 1.6 ? 3.6 v ambient temperature t a ?20 25 85 c notes: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v d = v a = 3.3 v and 25 c unless otherwise stated. parameters are tested in production unless otherwise stated. 3.2 power consumption specification table 2 power consumption specification parameter symbol test condition min typ max unit supply current (fm mode) i s enable = 1 disable = 0 ? 25 27 ma supply current (am mode) i s enable = 1 disable = 0 ? 24 26 ma power down current i pd enable = 0 disable = 1 ? 10 20 a interface power down current ip io sclk, rclk inactive enable = 0 ? 1.9 5 a free datasheet http://www..net/
bk1086/88 proprietary and confidential page 9 of 30 3.3 receiver characteristics table 3 fm receiver characteristics parameter test condition min typ max unit input frequency 64 ? 108 mhz sensitivity 2,3,4,5,6 (s+n)/n = 26 db ? 1.7 2.2 v emf lna input resistance 7 2.5 3 3.5 k ? input ip3 8 ? 92 ? db v emf am suppression 2, 3, 4, 5, 7 m = 0.3 40 45 ? db adjacent channel selectivity 200 khz 35 45 ? db alternate channel selectivity 400 khz 50 60 ? db audio output voltage 2, 3, 4, 7 ? 100 ? mv rms audio stereo separation 2, 4, 5, 7 30 ? ? db audio s/n 2, 3, 4, 5, 7, 55 ? db audio thd 2, 3, 5, 7, 10 ? 0.1 0.3 % de-emphasis time constant 11 50 75 s audio common mode voltage 12 enable = 1 0.8 0.9 1.0 v audio output load resistance single-ended ? 32 ? ? seek/tune time ? ? 60 ms/channel rssi offset input levels of 8 and 50 db v at rf input ?3 ? 3 db notes: 1. volume = maximum for all tests 2. f mod = 1 khz, 75 s de-emphasis 3. mono = 1, and l = r unless noted otherwise 4. f = 22.5 khz 5. b af = 300 hz to 15 khz, a-weighted 6. sensitivity without matching network 7. measured at v emf = 1 mv, f rf = 64 to 108 mhz 8. |f2 ? f1| > 2 mhz, f0 = 2 x f1 ? f2. agc is disabled by setting agcd = 1 9. the channel spacing is selected with the space [1:0] bits 10. f = 75 khz 11. the de-emphasis time constant is selected with the de bit 12. at lout and rout pins free datasheet http://www..net/
bk1086/88 proprietary and confidential page 10 of 30 table 4 am receiver characteristics parameter test condition min typ max unit long wave(am) 153 ? 279 khz medium wave(am) 520 ? 1710 khz frequency short wave(sw) 2.3 ? 21.85 mhz sensitivity 1,2,3 (s+n)/n = 26 db ? 20 v emf large signal voltage handling 300 mv rms power supply rejection ratio 40 ? db audio output voltage ? 100 ? mv rms audio s/n 1,2,3,5 55 ? db audio thd 1,2,3,5 ? 0.1 % medium wave(am) 180 600 antenna inductance long wave(lw) 2800 uh power up time from power down ? 150 ms notes: 1. fmod = 1khz , 30%modulation , a-weighted , 2 khz channel filter 2. b af = 300 hz to 15 khz, a-weighted 3. f rf = 1000khz 4. guaranteed by characterization 5. v in = 5 mv rms free datasheet http://www..net/
bk1086/88 proprietary and confidential page 11 of 30 3.4 i2c control interface characteristics table 4 i2c control interface characteristics parameter symbol test condition min typ max unit sclk frequency f scl ? ? 400 khz sclk low time t low 1.3 ? ? s sclk high time t high 0.6 s sclk input to sdio setup (start) t su:sta 0.6 ? ? s sclk input to sdio hold (start) t hd:sta 0.6 ? ? s sdio input to sclk setup t su:dat 100 ? ? ns sdio input to sclk hold t hd:dat ? ? 900 ns sclk input to sdio setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sdio output fall time t f:out ? ? 250 ns sdio input, sclk rise/fall time t f:in t r:in ? ? 200 ns sclk, sdio capacitive loading c b ? ? 60 pf input filter pulse suppression t sp ? ? 40 ns sclk sdio // // // start start stop t su:sta t hd:sta t low t high t r:in t f:in t sp t su:sto t buf t r:in t hd:dat t su:dat t f:in, ? t f:out figure 5 i2c control interface read and write timing diagram free datasheet http://www..net/
bk1086/88 proprietary and confidential page 12 of 30 3.5 3-wire control inte rface characteristics table 5 3-wire control interface characteristics parameter symbol test condition min typ max unit sclk frequency f clk 0 ? 2.5 mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk setup t s 20 ? ? ns sdio input to sclk hold t hsdio 10 ? ? ns sen input to sclk hold t hsen 10 ? ? ns sclk to sdio output valid t cdv read 2 ? 25 ns sclk to sdio output high z t cdz read 2 ? 25 ns sclk, sen, sdio, rise/fall time t r , t f ? ? 10 ns sclk sdio // sen t s t r t f t s t hsdio t high t low t hsen a6 a5-a0 r/w // // // d15 d14-d1 d0 address in data in figure 6 3-wire control interface write timing diagram sclk sdio // sen t s t s t hsdio t hsen a6 a5-a0 r/w // // // d15 d14-d1 d0 address in data out // // // // t cdv t cdz ?cycle bus turnaround figure 7 3-wire control interface read timing diagram free datasheet http://www..net/
bk1086/88 proprietary and confidential page 13 of 30 4 register definition register 00h. device id (0x8040) bit name default description [15:0] devid[15:0] 16?h8040 device id register 01h. chip id (0x1080) bit name default description [15:0] chipid[15:0] 16h?1080 chip id register 02h. power co nfiguration (0x0280) bit name default description [15] dsmute 1?h0 soft mute disable. 0 = soft mute enable. 1 = soft mute disable. [14] mutel 1?h0 mute l channel. 0 = l channel normal operation. 1 = l channel mute. [13] muter 1?h0 mute l channel. 0 = r channel normal operation. 1 = r channel mute. [12] mono 1?h0 mono. 0 = normal operation. 1 = force mono. [11] stereo 1?h0 stereo 0 = normal operation. 1 = force stereo. mono and stereo cannot be set to 1 simultaneously. [10] skmode 1?h0 seek mode 0 = wrap 1 = stop at the upper or higher band limit [9] seekup 1?h1 seek direction. 0 = seek down. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 14 of 30 1 = seek up. [8] seek 1?h0 seek 0 = disable 1 = enable seek a pos edge can start the seek process and during it seek should be 1 [7] skafcrl 1?h1 seek with afc rail 0 = during seeking, the channel is valid no matter whether afcrl is high or low. 1 = during seeking, the channel is invalid if afcrl is high. [6] disable 1?h0 power up disable 0 = normal operation 1 = power down [5:1] snr_ref[4:0] 5?h0 output snr adjustment. read snr = snr (calculated) ? snr_ref [0] enable 1?h0 power up enable 0 = power down 1 = normal operation note: only disable=0 and enable=1 can power on the device register 03h. channel (0x0000) bit name default description [15] tune 1?h0 tune 0 = disable 1 = enable note: a pos edge can start the tune process and during it tune must be 1 and seek must be 0 [14:0] chan[14:0] 15?h0 channel select the tuned frequency = band + chan * space register 04h. system configuration1 (0x1180) bit name default description [15] rdsien 1?h0 rds interrupt enable 0 = disable. 1 = enable. when register gpio2[1:0]=2?b01 and new rds come, a 5ms low pulse will appear at gpio2 [14] stcien 1?h0 seek/tune complete interrupt enable 0 = disable. 1 = enable. when register gpio2[1:0]=2?b01 and seek or tune finish, a 5ms low pulse will appear at gpio2 .both rdsien and stcien can be high free datasheet http://www..net/
bk1086/88 proprietary and confidential page 15 of 30 [13] afcinv 1?h0 afc invert 0 = normal afc into mixer 1 = reverse afc into mixer [12] rdsen 1?h1 rds enable 0 = disable rds. 1 = enable rds [11] de 1?h0 de-emphesisi 0 = 75us 1 = 50us [10:9] tcpilot 2?h0 the time used to cal the strength of pilot 00:4ms 01:8ms 10:16ms 11:32ms [8:6] blndadj [2:0] 3?h3 stereo/mono blend level adjustment. 000 = 31?49 rssi (0 dbuv) 001 = 34?52 rssi (+3 dbuv) 010 = 37?55 rssi (+6 dbuv) 011 = 40?58 rssi (+9 dbuv) 100 = 31?49 rssi (0 dbuv) 101 = 28?46 rssi (-3 dbuv) 110 = 25?43 rssi (-6 dbuv) 111 = 22?40 rssi (-9 dbuv) [5:4] gpio3[1:0] 2?h0 general purpose i/o 3. 00 = high impedance 01 = mono/stereo indicator (st) 10 = low 11 = high [3:2] gpio2[1:0] 2?h0 general purpose i/o 3. 00 = high impedance 01 = stc/rds interrupt. 10 = low 11 = high [1:0] gpio1[1:0] 2?h0 general purpose i/o 3. 00 = high impedance 01 = clk38mhz 10 = low 11 = high register 05h. system co nfiguration2 (0x3ddf) bit name default description [15:9] seekth [6:0] 7?h1e rssi seek threshold [8:7] band[1:0] 2?h3 band select am: 00: lw 153~279e3 fm:00: full 64~108e6 10: mw 520~1710e3 01: east europe 64~76e6 10: sw 2.3~21.85e6 10: japan 76~91e6 11: mw 522~1710e3 11: europe 87~108e6 (lw and sw band are only defined at BK1088) [6:5] space[1:0] 2?h2 channel spacing free datasheet http://www..net/
bk1086/88 proprietary and confidential page 16 of 30 am: 0: 1e3 fm: 0: 10e3 1: 5e3 1: 50e3 2: 9e3 2: 100e3 3: 10e3 3: 200e3 [4:0] volume [4:0] 5?h1f volume 0x00 is the lowest and 0x1f is highest (0dbfs). 2db each register 06h. system co nfiguration3 (0x01ef) bit name default description [15:14] smuter[1:0] 2?h0 soft mute attack/recover rate 00 = fastest 01 = fast 10 = slow 11= slowest [13:12] smutea[1:0] 2?h0 soft mute attenuation. 00 = 16db. 01 = 14db 10 = 12db, 11 = 10db [11] clksel 1?h0 clock select 0 = external clock input, 1= internal oscillator input. [10:4] sksnr[6:0] 7?h1e seek snr threshold. required channel snr for a valid seek channel [3:0] skcnt[3:0] 4?hf seek impulse detection threshold allowable number of impulse for a valid seek channel while setting all zeros means not use impulse number to judge the channel?s validity. register 07h. test1 (0x0900) bit name default description [15:14] reserved 2?h0 reserved [13] mode 1?h0 receiver mode select 0 = fm receiver 1 = am receiver [12] siq 1?h0 if i/q signal switch. 0 = normal operation 1 = reversed i/q signal [11] impen 1?h1 impulse remove enable 0 = disable 1 = enable [10] bpde 1?h0 de-emphasis bypass 0 = normal operation 1 = bypass de-emphasis [9:8] impth[1:0] 2?h1 threshold of impulse detect. 00 = toughest free datasheet http://www..net/
bk1086/88 proprietary and confidential page 17 of 30 11 = loosest [7:3] stgain [4:0] 5?h0 stereo l/r gain adjustment, sighed value 00000 = 0 db 01111=15db 10000= -16db 11111= -1db for stereo separation optimization [2:0] fmgain [2:0] 3?h0 the gain of frequency demodulated. 000 = 0db 011= +18db 100= 0db 111= -18db register 08h. test2 (0x ac90) bit name default description [15] afcen 1?h1 afc enable 0 = disable 1 = enable [14:13] tcsel[1:0] 2?h1 afc/rssi/snr calculate rate 00 = fastest 11 = slowest. 4x times each [12] sel25k 1?h0 afcrl threshold 0 = channel space/2 1 = 25khz [11] ave 1?h1 afc average 0 = use the instant afc value 1 = use the average afc value [10:9] var[1:0] 2?h2 variation threshold for average afc calculation 00 = disable 01 = the toughest 11 = the loosest [8:7] range [1:0] 2?h1 afc average range 00 = the toughest 11 = the loosest [6:0] afcrssit h[6:0] 7?h10 rssi threshold for instant afc updating register 09h. status1 (0x0000) bit name default description [15:7] afc[8:0] 9?h000 the afc value. unit am 0.15k hz, fm 0.6k hz [6:0] snr[6:0] 7?h00 the snr value.( in db) free datasheet http://www..net/
bk1086/88 proprietary and confidential page 18 of 30 register 0ah. status2 (0x0000) bit name default description [15] rdsr 1?h0 rds ready indicator 0 = not ready 1 = ready keep high for 40ms after new rds is received [14] stc 1?h0 seek/tune complete 0 = not complete 1 = complete [13] sf/bl 1?h0 seek fail/band limit 0 = seek successful. 1 = seek fail/band limit reached [12] afcrl 1?h0 afc rail 0 = afc not railed 1 = afc railed [11:8] cntimp 4?h0 impulse number [7] st 1?h0 stereo indicator [6:0] rssi[6:0] 7?h00 rssi value register 0bh. read channel (0x0000) bit name default description [15] reserved 1?h0 reserved [14:0] readcha n[14:0] 15?h0000 read channel provides the current working channel register 0ch. rds1 (0x0000) bit name default description [15:0] rdsa[15:0] 16?h0000 the first register of rds received register 0dh. rds2 (0x0000) bit name default description [15:0] rdsb[15:0] 16?h0000 the second register of rds received free datasheet http://www..net/
bk1086/88 proprietary and confidential page 19 of 30 register 0eh. rds3 (0x0000) bit name default description [15:0] rdsc[15:0] 16?h0000 the third register of rds received register 0fh. rds4 (0x0000) bit name default description [15:0] rdsd[15:0] 16?h0000 the fourth register of rds received when read register 10h. boot configuration1 (0x7b11) bit name default description [15:0] reserved 16?h7b11 reserved. register 11h. boot configuration2 (0x0080) bit name default description [15:0] reserved 16?h0080 reserved. register 12h. boot configuration3 (0x4000) bit name default description [15:0] reserved 16?h4000 reserved. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 20 of 30 register 13h. boot configuration4 (0x3e00) bit name default description [15:0] reserved 16?h3e00 reserved. register 14h. boot configuration5 (0x0000) bit name default description [15] skmute 1?h0 0: disable soft mute when seeking 1: enable soft mute when seeking [14] afcmute 1?h0 0: disable soft mute when afcrl is high 1: enable soft mute when afcrl is high [13:7] snrmth[6:0] 7?h00 the mute threshold based on snr [6:0]] rssimth[6:0 7?h00 the mute threshold based on rssi register 15h. boot configuration6 (0x0000) bit name default description [15:0] reserved 16?h8000 reserved. register 16h. boot configuration7 (0x0400) bit name default description [15:0] reserved 16?h0400 reserved. register 17h. boot configuration8 (0x0001) bit name default description [15:0] reserved 16?h0001 reserved. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 21 of 30 register 18h. boot configuration9 (0x143c) bit name default description [15:0] reserved 16?h143c reserved. register 19h. boot configuration10 (0x4351) bit name default description [15:0] reserved 16?h4351 reserved. do not write anytime. register 1ah. boot configuration11 (0x0000) bit name default description [15:9] reserved 7?h00 reserved. [8:0] ant_sel[8:0] 9?h000 antenna varactor tune register 1bh. analog configuration1 (0x0000) bit name default description [15] freq_sel[0] 1?h0 reference clock divider control ,refer to reg1d default 0 for 32.768khz reference input. [14:0] reserved 15?h0000 reserved. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 22 of 30 register 1ch. analog configuration2 (0x0000) bit name default description [15] freq_sel[1] 1?h0 reference clock divider control ,refer to reg1d default 0 for 32.768khz reference input. [14:0] reserved 15?h0000 reserved. register 1dh. analog configuration2 (0x0000) bit name default description [15] freq_sel[17:2] 16?h0000 reference clock divider control , freq_sel[17:0] = hex |ref frequency/512+0.5| default 16 for 32.768khz reference. register 1eh - register 28h. internal test registers are not accessible for user. initial value and procedure will be provided separately by beken. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 23 of 30 5 pin assignment figure 8 pin assignment for bk1086/88 qfn24 4x4 mm package pin number(s) name description 1,5,14,17,24, gnd pad gnd ground. connect to ground plane on pcb 2 fmi fm rf input. 3 rfgnd rf ground. 4 ami mw/sw/lw rf input. 7 mode control interface selection mode pin is low , i 2 c mode mode pin is high , spi mode 8 sen serial communications enable. (active low) 9 sclk clock for serial communications. 10 sdio serial data input/output. 11 rclk 32.768khz - 38.4mhz external reference clock input/32.768khz oscillator input. 12 vio power supply for i/o. 13 vd power supply for digital. 15 rout right audio output. 16 lout left audio output. 18 va power supply for analog. 19,20,21 gpio1,2,3 general purpose input/output. 6,22,23 nc not connect. gnd fmi rfgnd ami gnd nc mode s e n sclk sdio rclk vio vd gnd rout lout gnd va gpio3 gpio2 gpio1 nc nc gnd 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 19 20 21 22 23 24 gnd pad bk1086/88 free datasheet http://www..net/
bk1086/88 proprietary and confidential page 24 of 30 6 typical application schematic figure 9 bk1086/88 with headphone antenna application notes 1. j1: common 32 ? resistance headphone. 2. u1:bk1086/88 chip. 3. fm choke (l headphone and c3) for lna input match with the headphone. 4. pin nc (6, 22, and 23) should be leaved floating. 5. place c6, c7 close to chip pin. 6. all grounds connect directly to gnd plane on pcb. 7. keep the fmi and ami trace as short as possible. 8. keep the wire from fmi to headphone as short as possible and must put it on the surface of the pcb. 9. when use crystal to generate the reference clock, please refer to the option 1(crystal connection). 1 2 6 5 4 3 13 14 15 16 17 18 7 9 8 10 11 12 24 23 22 21 20 19 gnd fmi mode nc rfgnd gnd ami sen sclk sdio rclk vio avdd gnd dvdd lout gnd rout gnd nc nc gpio1 gpio2 gpio3 hp jack l ferrite l headphone c1 c2 c3 c5 10uf fb1 =2.5k@100mhz v battary 2.7 to 5.5v c6 100nf c7 100nf u1 bk1086 /88 mode sen sclk sdio rclk vio c4 10uf fb2 =2.5k@100mhz c10 100pf c11 100pf c12 rclk option 1 crystal connection 32.768khz free datasheet http://www..net/
bk1086/88 proprietary and confidential page 25 of 30 7 package information qfn 4x4 24pin packages are available for bk1086/88. detail information of the package follows: figure 10 qfn 4x4 24 pin package diagram table 6 qfn 4x4 24 pin package dimensions parameter min typ max unit a 0.70 0.75 0.80 mm a1 0.00 - 0.05 mm a3 0.20 ref mm d 3.95 4.00 4.05 mm e 3.95 4.00 4.05 mm b 0.20 0.25 0.30 mm l 0.35 0.40 0.45 mm d2 2.30 2.45 2.55 mm e2 2.30 2.45 2.55 mm e 0.50 ref mm free datasheet http://www..net/
bk1086/88 proprietary and confidential page 26 of 30 soldering layer content content width unit ni 0.5-2.0 um pd 0.02-0.15 um au 0.003-0.015 um storage caution 1. calculated shelf life in vacuum sealed bag 12 months at<40 and 90% relative humidity(rh). 2. peak package body temperature 260 . 3. after vacuum sealed bag is opened ,devices that will be subjected to reflow solder or other high temperature process must a) mounted within 168 hours of factory conditions<40 /60%. b) stored at 10% rh. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 27 of 30 8 solder reflow profile figure 11 classification reflow profile profile feature specification average ramp-up rate (tsmax to tp) 3c/second max. temperature min (tsmin) 150c temperature max (tsmax) 200c pre_heat time (ts) 60-180 seconds temperature (tl) 217c time maintained above time (tl) 60-150 seconds peak/classification temperature (tp) 260c time within 5c of actual peaktemperature (tp) 20-40 seconds ramp-down rate 6 6c/second max. time 25c to peak temperature 8 8 minutes max. rohs compliant the product does not contain lead, mercury, cadmium, hexavalent chromium, pbb&pbde content in accordance with directive 2002/95/ec(rohs). esd sensitivity integrated circuits are esd sensitive and can be damaged by static electricity. proper esd techniques should be used when handling these devices. free datasheet http://www..net/
bk1086/88 proprietary and confidential page 28 of 30 9 order information part number package packing moq (ea) bk1086qb qfn24 tape reel 3k BK1088qb qfn24 tape reel 3k remark: moq: minimum order quantity free datasheet http://www..net/
bk1086/88 proprietary and confidential page 29 of 30 10 additional reference resource ? universal application guide ? evb quick-start guide free datasheet http://www..net/
bk1086/88 proprietary and confidential page 30 of 30 11 revision history version change summary data author rev.0.1 initial draft 06-29-2009 jw rev.0.2 02-04-2010 jw rev.1.0 formal release version 09-15-2010 jw free datasheet http://www..net/

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